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STM6321/6322 STM6821/6822/6823/6824/6825
5-pin Supervisor with watchdog timer and push-button reset
Features

Precision VCC monitoring of 5, 3.3, 3, or 2.5V power supplies RST Outputs (active-low, push-pull or open drain) RST Outputs (active-high, push-pull) Reset pulse width of 1.4ms, 200ms and 240ms (typ) (a) Watchdog timeout period of 1.6s (typ) (a) Manual reset input (MR) Low supply current - 3A (typ) Guaranteed RST (RST) assertion down to VCC = 1.0V Operating temperature: -40 to +85C (industrial grade) RoHS Compliance Lead-free components are compliant with the RoHS directive. SOT23-5 (WY)
Table 1.
Device options
Reset output Watchdog input Manual reset input
Part number
Active-low (push-pull)
Active-high (push-pull)
Active-low (open drain)
STM6321 STM6322 STM6821 STM6822 STM6823 STM6824 STM6825

a.
Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
May 2007
Rev 7
1/26
www.st.com 1
Contents
STM6321/6322STM6821/6822/6823/6824/6825
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825 . . 7 Active-low, open drain reset output (RST) - STM6321/6322/6822 . . . . . 7 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Active-high reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Open drain RST output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Push-button reset input (STM6322/6821/6822/6823/6825) . . . . . . . . . . . 11 Watchdog input (STM6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.1 2.5.2 Watchdog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ensuring a valid reset output down to VCC = 0V . . . . . . . . . . . . . . . . . . 11
2.6
Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 12
3 4 5 6 7 8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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STM6321/6322STM6821/6822/6823/6824/6825
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SOT23-5 - 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 22 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of figures
STM6321/6322STM6821/6822/6823/6824/6825
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM6321/6322/6822 open drain RST output with multiple supplies . . . . . . . . . . . . . . . . . 10 Ensuring RST valid to VCC = 0, (active-low push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 12 Ensuring RST valid to VCC = 0, (active-high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12 Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC-to-Reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MR-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normalized power-up watchdog time-out period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage output low vs. ISINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage output high vs. ISOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SOT23-5 - 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 22
4/26
STM6321/6322STM6821/6822/6823/6824/6825
Summary description
1
Summary description
The STM6xxx Supervisors are self-contained devices which provide microprocessor supervisory functions. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM6322/6825) and/or a push-button (MR) reset input. These devices are available in a standard 5-pin SOT23 package. Figure 1. Logic diagram (STM6821/6822/6823)
VCC
WDI STM6XXX MR RST (RST)(1)
VSS
AI09128
1. For STM6821 only.
Figure 2.
Logic diagram (STM6321/6322/6824/6825)
VCC
RST (WDI)(1) MR STM6XXX RST
VSS
AI09129
1. For STM6321/6824.
Table 2.
MR WDI RST RST VCC VSS
Signal names
Push-button Reset Input Watchdog Input Active-low Reset Output Active-high Reset Output Supply voltage Ground
5/26
Summary description Figure 3.
STM6321/6322STM6821/6822/6823/6824/6825 STM6822/6823 SOT23-5 connections
SOT23-5 RST VSS MR
(1)
1 2 3
5 4
VCC WDI
AI09130a
1. Open drain for STM6822.
Figure 4.
STM6821 SOT23-5 connections
SOT23-5 RST(1) VSS MR 1 2 3 5 4 VCC WDI
AI12285
1. Push-pull only.
Figure 5.
STM6322/6825 SOT23-5 connections
SOT23-5 RST VSS
(1)
RST(2)
1 2 3
5 4
VCC MR
AI09131a
1. Open drain for STM6322. 2. Push-pull only.
Figure 6.
STM6321/6824 SOT23-5 connections
SOT23-5 RST(1) VSS RST(2) 1 2 3 5 4 VCC WDI
AI12286
1. Open drain for STM6321. 2. Push-pull only.
6/26
STM6321/6322STM6821/6822/6823/6824/6825
Summary description
1.1
1.1.1
Pin descriptions
Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.2
Active-low, open drain reset output (RST) - STM6321/6322/6822
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. Connect a pull-up resistor to supply voltage.
1.1.3
Push-button reset input (MR)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal 52k pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused.
1.1.4
Watchdog input (WDI)
If WDI remains high or low for at least 1.6s, the internal watchdog timer expires and reset is asserted. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function CAN be disabled if WDI is left unconnected or is connected to a tri-state buffer output.
1.1.5
Active-high reset output (RST)
Active-high, push-pull reset output; inverse of RST. Table 3. Pin functions
Pin STM6822 STM6823 1 3 4 -- 5 2 STM6821 -- 3 4 1 5 2 STM6321 STM6824 1 -- 4 3 5 2 STM6322 STM6825 1 4 -- 3 5 2 RST MR WDI RST VCC VSS Active-Low Reset Output Push-button Reset Input Watchdog Input Active-High Reset Output Supply Voltage Ground Name Function
7/26
Summary description
STM6321/6322STM6821/6822/6823/6824/6825
Figure 7.
Block diagram (STM6821/6822/6823)
WDI Transitional Detector WATCHDOG TIMER trec Generator
WDI VCC VCC
VRST
COMPARE
RST (RST)
(1,2)
MR
AI09132a
1. Push-pull for STM6823, open drain for STM6822. 2. Active-high (push-pull) for STM6821.
Figure 8.
Block diagram (STM6321/6824)
WDI Transitional Detector WATCHDOG TIMER trec Generator RST(1) RST
(2) A12287
WDI VCC
VRST
COMPARE
3. Acive-low (open drain) for STM6321, active-low (push-pull) for STM6824. 4. Push-pull only.
Figure 9.
Block diagram (STM6322/6825)
VCC VCC VRST COMPARE RST(1) RST
(2)
trec Generator
MR
AI12288
1. Active-low (open drain) for STM6322, active-low (push-pull) for STM6825. 2. Push-pull only.
8/26
STM6321/6322STM6821/6822/6823/6824/6825
Summary description
Figure 10. Hardware hookup
VCC VCC
0.1F
STM6XXX
From Microprocessor
WDI
(1)
Push-button
MR(2) RST (RST)
(3)
To Microprocessor Reset To Microprocessor Reset
RST(4)
AI09133
1. For STM6321/6821/6822/6823/6824 2. For STM6322/6821/6822/6823/6825 3. For STM6821/ (RST output only) 4. For STM6321/6322/6824/6825 (both RST and RST outputs)
9/26
Operation
STM6321/6322STM6821/6822/6823/6824/6825
2
2.1
Operation
Reset output
The STM6xxx Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1V for TA = 0C to 85C. During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low for the reset time-out period, trec. After this interval reset is de-asserted. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
2.2
Open drain RST output
The STM6321/6322/6822 have an active-low, open drain reset output. This output structure will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply voltage up to 6V (see Figure 11). Select a resistor value large enough to register a logic low, and small enough to register a logic high while supplying all input current and leakage paths connected to the reset output line. A 10k pull-up resistor is sufficient in most applications. Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
3.3V 5.0V
VCC STM6XXX MR(1) WDI(2) RST(3) RST GND
AI09137
10k
5V System
1. STM6322/6822 2. STM6321/6822 3. STM6321/6322
10/26
STM6321/6322STM6821/6822/6823/6824/6825
Operation
2.3
Push-button reset input (STM6322/6821/6822/6823/6825)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 25 on page 19) after it returns high. The MR input has an internal 52k pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1F capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used.
2.4
Watchdog input (STM6321/6821/6822/6823/6824)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6sec), the reset is asserted. The internal watchdog timer is cleared by either: 1. 2. a reset pulse, or by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns.
The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting. Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10A and the maximum allowable load capacitance is 200pF.
2.5
2.5.1
Applications information
Watchdog input current
The WDI input is internally driven through a buffer and series resistor from the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period. When high, WDI can draw as much as 160A. Pulsing WDI high at a low duty cycle will reduce the effect of the large input current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog time-out period by a low-high-low pulse from the counter chain.
2.5.2
Ensuring a valid reset output down to VCC = 0V
The STM6xxx Supervisors are guaranteed to operate properly down to VCC = 1V. In applications that require valid reset levels down to VCC = 0, a pull-down resistor to activelow outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active-high outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid while the reset output can no longer sink or source current. This scheme does not work with the open drain outputs of the STM6321/6322/6822. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100k is adequate.
11/26
Operation
STM6321/6322STM6821/6822/6823/6824/6825 Figure 12. Ensuring RST valid to VCC = 0, (active-low push-pull outputs)
STM6XXX VCC GND RST R1
AI09138
VCC
Figure 13. Ensuring RST valid to VCC = 0, (active-high, push-pull outputs)
STM6XXX VCC GND RST VCC R1
AI09139
1. This configuration does not work on open drain outputs of the STM6321/6322/6822.
2.6
Interfacing to microprocessors with bi-directional reset pins
Microprocessors with bi-directional reset pins can contend with the STM6321 / 6322 / 6821 / 6822 / 6823 / 6824 / 6825 reset output. For example, if the reset output is driven high and the microprocessor wants to pull it low, signal contention will result. To prevent this from occurring, connect a 4.7k resistor between the reset output and the microprocessor's reset I/O as in Figure 14. Figure 14. Interfacing to microprocessors with bi-directional reset I/O
Buffered Reset to other System Components
VCC STM6XXX 4.7k RST RST
VCC Microprocessor
GND
GND
AI09135
12/26
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
3
Typical operating characteristics
Figure 15. VCC-to-Reset output delay vs. temperature
35 30
Reset Output Delay (s)
25 20 15 10 5 0 -40
-20
0
20
40
60
80
AI09627a
Temperature (C)
Figure 16. Supply current vs. temperature
7 6
Supply Current (A)
5 4 3 2 1 0 -40
VCC = 3V VCC = 5V
-20
0
20
40
60
80
AI09628a
Temperature (C)
13/26
Typical operating characteristics
STM6321/6322STM6821/6822/6823/6824/6825
Figure 17. MR-to-reset output delay vs. temperature
600
Reset Output Delay (ns)
500 400 300 200 100 0 -40
-20
0
20
40
60
80
AI09669
Temperature (C)
Figure 18. Normalized power-up trec vs. temperature
1.05
Normalized Power-up trec
1.04 1.03 1.02 1.01 1.00 0.99 -40
-20
0
20
40
60
80
AI09670
Temperature (C)
14/26
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 19. Normalized reset threshold voltage vs. temperature
1.05 1.04
Normalized Reset Threshold Voltage
1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 -40
-20
0
20
40
60
80
AI09631a
Temperature (C)
Figure 20. Normalized power-up watchdog time-out period
Normalized Watchdog Time-out Period
1.05 1.04 1.03 1.02 1.01 1.00 0.99 -40 -20 0 20 40 60 80
AI09671
Temperature (C)
15/26
Typical operating characteristics
STM6321/6322STM6821/6822/6823/6824/6825
Figure 21. Voltage output low vs. ISINK
0.35
0.30
0.25
VOUT (V)
0.20
VCC = 2.9V
0.15
0.10
0.05
0.00 0 1 2 3 4 5 6
AI09634a
ISINK (mA)
Figure 22. Voltage output high vs. ISOURCE
2.92 2.90 2.88 2.86
VOUT (V)
2.84
VCC = 2.9V
2.82 2.80 2.78 2.76 2.74 0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
AI09635a
ISOURCE (mA)
16/26
STM6321/6322STM6821/6822/6823/6824/6825
Typical operating characteristics
Figure 23. Maximum transient duration vs. reset threshold overdrive
35 30
Transient Duration (s)
25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 180 200
AI09637a
S Z L
Reset Threshold Overdrive (mV)
17/26
Maximum rating
STM6321/6322STM6821/6822/6823/6824/6825
4
Maximum rating
Stressing the device above the rating listed in the Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol TSTG TSLD
(1)
Absolute maximum ratings
Parameter Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltage Supply Voltage Output Current Power Dissipation Value -55 to 150 260 -0.3 to VCC +0.3 -0.3 to 7.0 20 320 Unit C C V V mA mW
VIO VCC IO PD
1. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
18/26
STM6321/6322STM6821/6822/6823/6824/6825
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions
Parameter VCC Supply Voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages STM6xxx 1.0 to 5.5 -40 to 85 5 0.2 to 0.8VCC 0.3 to 0.7VCC Unit V C ns V V
Figure 24. AC Testing input/output waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Figure 25. MR timing waveform
MR tMLRL RST
(1)
tMLMH
trec
AI07837a
1. RST for STM6322/6821/6825.
Figure 26. Watchdog timing
VCC
RST
trec
WDI
tWD
AI09136
19/26
DC and AC parameters Table 6.
Sym VCC
STM6321/6322STM6821/6822/6823/6824/6825
DC and AC characteristics
Alternative Description Operating Voltage VCC Supply Current (MR and WDI unconnected) T/S/R/Z (VCC < 3.6V) L/M (VCC < 5.5V) T/S/R/Z (VCC < 3.6V) L/M (VCC < 5.5V) 0V = VIN = VCC WDI = VCC, time average WDI = GND, time average VCC > VRST, Reset not asserted VRST > 4.0V VRST < 4.0V
(4)
Test Condition (1)
Min 1.2 (2)
Typ
Max 5.5
Unit V A A A A A A A
4 6 3 3 -1 120 -20 -1 2.0 0.7VCC 0.7VCC -15
12 17 8 12 +1 160
ICC
VCC Supply Current (MR unconnected; STM6322/6825) Input Leakage Current
ILI
Input Leakage Current (WDI)(3) Open Drain Reset Output Leakage Current Input High Voltage (MR) Input High Voltage (WDI) Input Low Voltage (MR) Input Low Voltage (WDI) (4)
ILO VIH VIH VIL VIL
+1
A V V V
VRST (max) < VCC < 5.5V VRST > 4.0V VRST < 4.0V VRST (max) < VCC < 5.5V VCC 1.0V, ISINK = 50A, Reset asserted
0.8 0.3VCC 0.3VCC 0.3 0.3 0.3 0.4 0.3 0.4 0.8VCC 0.8VCC 0.8VCC 0.8VCC 0.8VCC 0.8VCC
V V V V V V V V V V V V V V V
Output Low Voltage (RST; Push-pull or Open Drain) VOL
VCC 1.2V, ISINK = 100A, Reset asserted VCC 2.7V, ISINK = 1.2mA, Reset asserted VCC 4.5V, ISINK = 3.2mA, Reset asserted
Output Low Voltage (RST; Push-pull Only)
VCC 2.7V, ISINK = 1.2mA, Reset not asserted VCC 4.5V, ISINK = 3.2mA, Reset not asserted VCC 2.7V, ISOURCE = 500A, Reset not asserted VCC 4.5V, ISOURCE = 800A , Reset not asserted VCC 1.0V, ISOURCE = 1A, Reset asserted (0C to 85C) VCC 1.5V, ISOURCE = 100A, Reset asserted VCC 2.55V, ISOURCE = 500A, Reset asserted VCC 4.25V, ISOURCE = 800A, Reset asserted
Output High Voltage (RST)
VOH Output High Voltage (RST)
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STM6321/6322STM6821/6822/6823/6824/6825
DC and AC parameters
Sym
Alternative
Description
Test Condition (1)
Min
Typ
Max
Unit
Reset Thresholds STM6xxxL STM6xxxM STM6xxxT VRST(5) Reset Threshold STM6xxxS STM6xxxR STM6xxxZ (6) Reset Threshold Hysteresis VCC to RST Delay (VRST - VCC = 100mV, VCC falling at 1mV/s) A trec
(7)
25C -40 to 85C 25C -40 to 85C 25C -40 to 85C 25C -40 to 85C 25C -40 to 85C 25C -40 to 85C
4.561 4.514 4.314 4.270 3.040 3.000 2.890 2.857 2.590 2.564 2.280 2.250
4.630 4.390 3.080 2.930 2.630 2.320 10 5 20
4.699 4.746 4.446 4.490 3.110 3.150 2.960 3.000 2.660 2.696 2.350 2.380
V V V V V V V V V V V V mV mV s
L/M versions T/S/R/Z versions
1 140 240
1.4 200 280 40
2 280 480
ms ms ms ppm /C
Reset Pulse Width Reset Threshold Temperature Coefficient
Blank J
Push-button Reset Input tMLMH tMLRL tMR tMRD MR Pulse Width MR to RST Output Delay MR Glitch Immunity MR Pull-up Resistor Watchdog Timer tWD (7) Watchdog Timeout Period WDI Pulse Width 1.12 50 1.60 2.24 s ns 35 1 500 100 52 75 s ns ns k
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V for "L/M" versions; VCC = 2.7 to 3.6V for "T/S/R" versions; and VCC = 2.1 to 2.75V for "Z" version (except where noted). 2. VCC (min) = 1.0V for TA = 0 to +85C. 3. WDI input is designed to be driven by a three-state output device. To float WDI, the "high-impedance mode" of the output device must have a maximum leakage current of 10A and a maximum output capacitance of 200pF. The output device must also be able to source and sink at least 200A when active. 4. WDI is internally serviced within the watchdog period if WDI is left unconnected. 5. The leakage current measured on the RST pin is tested with the reset asserted (output high impedance). 6. Contact local sales office for availability. 7. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
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Package mechanical data
STM6321/6322STM6821/6822/6823/6824/6825
6
Package mechanical data
Figure 27. SOT23-5 - 5-lead small outline transistor package mechanical drawing
E
A1
e D D1
B
A2 C K A CP F L
SOT23-5
1. Drawing is not to scale.
Table 7.
Symb
SOT23-5 - 5-lead small outline transistor package mechanical data
mm Typ Min 0.900 Max 1.450 0.150 1.050 0.400 0.150 2.900 1.900 2.800 0.950 1.600 1.500 0 0.350 0.100 1.750 10 0.600 0.0138 2.600 3.000 0.900 0.350 0.090 2.800 1.300 0.500 0.200 3.000 0.0413 0.0157 0.0059 0.1142 0.0748 0.1102 0.0374 0.0630 0.0591 0 0.0039 0.0689 10 0.0236 0.1024 0.1181 0.0354 0.0138 0.0035 0.1102 Typ 0.0472 inches Min 0.0354 Max 0.0571 0.0059 0.0512 0.0197 0.0079 0.1181
A A1 A2 B C D D1 E e F K L
1.200
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STM6321/6322STM6821/6822/6823/6824/6825
Part numbering
7
Part numbering
Table 8.
Example: Device Type STM6xxx Reset Threshold Voltage L: VRST = 4.514 to 4.746V M: VRST = 4.270 to 4.490V T: VRST = 3.000 to 3.150V S: VRST = 2.850 to 3.000V R: VRST = 2.564 to 2.696V Z: VRST = 2.250 to 2.380V (1) Reset Pulse Width (2) A: trec = 1 to 2ms Blank: trec = 140 to 280ms J: trec = 240 to 480ms Package WY = SOT23-5 Temperature range 6 = -40 to 85C Shipping method E = ECOPACK Package, Tubes F = ECOPACK Package, Tape & Reel
Ordering information scheme
STM6xxx L WY 6 E
1. Contact local sales office for availability. 2. Contact local sales office for availability. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Part numbering
STM6321/6322STM6821/6822/6823/6824/6825
Table 9.
Marking description
Reset threshold (V) 4.630 4.390 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 3.080 2.930 2.930 2.630 2.630 4.630 4.390 3.080 2.930 2.630 4.630 4.390 3.080 2.930 2.630 Reset pulse width (ms) 200 1.4 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 280 200 280 200 280 200 200 200 200 200 200 200 200 200 200 200 Topside marking 5AUx 5CRx 5AVx 5AWx 5AXx 5AYx 5BAx 5BBx 5BCx 5BDx 5BEx 5BGx 5BHx 5BJx 5BKx 5BLx 5BNx 5BPx 5BQx 5BRx 5BSx 5BUx 5BVx 5CMx 5BWx 5CNx 5BXx 5CPx 5BYx 5CAx 5CBx 5CCx 5CDx 5CEx 5CGx 5CHx 5CJx 5CKx 5CLx
Part number STM6321LWY6F STM6321MAWY6F STM6321MWY6F STM6321TWY6F STM6321SWY6F STM6321RWY6F STM6322LWY6F STM6322MWY6F STM6322TWY6F STM6322SWY6F STM6322RWY6F STM6821LWY6F STM6821MWY6F STM6821TWY6F STM6821SWY6F STM6821RWY6F STM6822LWY6F STM6822MWY6F STM6822TWY6F STM6822SWY6F STM6822RWY6F STM6823LWY6F STM6823MWY6F STM6823TJWY6F STM6823TWY6F STM6823SJWY6F STM6823SWY6F STM6823RJWY6F STM6823RWY6F STM6824LWY6F STM6824MWY6F STM6824TWY6F STM6824SWY6F STM6824RWY6F STM6825LWY6F STM6825MWY6F STM6825TWY6F STM6825SWY6F STM6825RWY6F
Note:
Where "x" = Assembly Work Week (A to Z), such that "A" = WW01-02, "B" = WW03-04, and so forth.
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STM6321/6322STM6821/6822/6823/6824/6825
Revision history
8
Revision history
Table 10.
Date August 25, 2004 15-Dec-04 10-Mar-05 17-Jun-05 11-Apr-06 11-Aug-2006 25-May-2007
Document revision history
Revision 1.0 2.0 3.0 4.0 5 6 7 First Draft Update characteristics (Figure 15, 16, 17; Table 6, and 8) Document promoted to Datasheet status Package marking update (Table 9) Update characteristics, Lead-free text, availability (Figure 3, 4, 5, 6, 7, 8, and 9; Table 1, 6, 8, and 9) Update Summary description, Table 8, and 9. Formatting changes, updated Table 9. Changes
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STM6321/6322STM6821/6822/6823/6824/6825
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